1. Field of the Invention
The present invention relates to a computer system provided with key control protection by a storage key. More particularly, it relates to a cache control device for controlling the operations of the cache, and a method thereof.
2. Description of the Related Art
A storage key is information for protecting the contents of a main storage of an information processing device from an improper access, and the key is created for each page of the main storage. This storage key consists of, for example, an access control bit (four bits), a fetch protection bit, a reference bit, and a change bit.
FIG. 1A is a block diagram showing a conventional information processing unit that has a storage key. The information processing unit of FIG. 1A includes a CPU (Central Processing Unit) instruction computation unit 31, a CPU memory unit 32, a main storage 33, and a key storage 41. The CPU memory unit 32 includes two caches 34, a control device 35, a main memory access validity detection circuit 36, two TLBs (Translation Lookaside Buffers) 37, two key buffers 38, a DAT (Dynamic Address Translation) 39, and a key access port 40.
TLB 37 is provided to speed up address translation, and a correspondence relation between a logical address and a physical address is registered or stored in TLB 37. The key buffer 38 is provided to speed up a key access, and a storage key is registered or stored in the key buffer 38. Here, the key accessing process demands or request a storage key stored in the key storage 41, thereby obtaining the key. Further, the cache 34 is provided to speed up a main memory access, thereby storing data faster.
One of the two caches 34 stores instructions as data, while the other stores operands as data. Regarding TLBs 37 and key buffers 38, one is used for instructions, while the other is used for operands. DAT 39 transforms an assigned logical address into a physical address.
The validity detection circuit 36 checks the validity of the main memory access, using a storage key registered in the key buffer 38 and an access key transmitted from the CPU instruction computation unit 31. The Key access port 40 stores a storage key transmitted from the key storage 41, and transfers it to the key buffer 38.
FIG. 1B is a timing chart of the cache control in the information processing unit of FIG. 1A. FIG. 1C is a flowchart showing the outline of the cache control. When a main memory access demand (request) is issued from the CPU instruction computation unit 31, a determination is made as to whether the physical address that is a translation result of the logical address associated with the demand is registered or stored in TLB 37 (hit or miss) (step S11).
When the physical address is not registered, TLB 37 reports a TLB miss to the control device 35, and then the control device 35 demands address translation from DAT 39(step S12). After the address translation process is carried out by DAT 39, the control device 35 demands or requests a storage key from the key storage 41 (step S13), and waits for a key arrival report (step S13).
When the storage key arrives at the key access port 40, this arrival triggers the registration or storage of a physical address that is the translation result of DAT 39. In TLB 37, and also the registration of a storage key of the key access port 40, in the key buffer 38 (step S15). Then, DAT 39 is released (step S16).
Then, the control device 35 resumes the process for a main memory access demand or access request. Since the physical address is registered in TLB 37, TLB 37 reports a TLB hit to the control device 35, and the control device 35 retrieves the cache 34 using this physical address output by TLB 37. In this way, it is determined whether data (instruction or operand) is stored or registered (hit or miss) in the cache 34 (step S17).
If data is not registered or stored, a data demand or request is issued to the main storage 33, and the arrived data is registered in the cache 34 (step S18). Then, the process for the main memory access demand is resumed. If data is registered, the cache 34 transmits the data, and reports a cache hit to the control device 35.
The CPU instruction computation unit 31 determines in advance whether a main memory access demand requires protection (key control protection) using a storage key, and it transmits the demand that differs according to the determination result to the CPU memory unit 32. Then, the CPU memory unit 32 determines whether a key check is required by the validity detection circuit 36 on the basis of a type of the demand (step S19). At the same time as the TLB hit, a validity detection circuit 36 reads out a storage key that is registered or stored in the key buffer 38, and it checks the validity of the access by comparing this key with an access key received from the CPU instruction computation unit 31 (step S20).
Specifically, when key control protection is not required, the CPU instruction computation unit 31 transmits to the CPU memory unit 32, a signal INH_KEY_CHECK for disregarding the check result of the validity detection circuit 36. The CPU memory unit 32 is configured to disregard the check result when this signal is on (logic value 1).
If the main memory access demand or access results in a cache hit, and the validity of access is admitted or acknowledged, data is transmitted to the CPU instruction computation unit 31 (step S21). The control device 35 transmits a data transfer report and a completion report to the CPU instruction computation unit 31, and completes the main memory access process. At this time, the result of the check or check result of the validity detection circuit 36 is transmitted to the CPU instruction computation unit 31 as a key protection exception signal. If the key protection exception signal is off (logic value 0) when the completion report is transmitted, the transmitted data comes into effect or is to be used.
If the validity of access is not admitted or acknowledged at step S20, the key protection exception signal becomes on, an exception report is transmitted to the CPU instruction computation unit 31 (step S22).
However, the above-mentioned conventional cache control has the following problems.
During conventional control, a main memory access is executed via a main memory access demand or request that requires key control protection, the validity of the access is checked for the obtained data, and the checked data is transmitted after the validity of access is admitted or acknowledged. Because of this, when a key access is required for the main storage, the device should wait for the arrival of the storage key, so that it takes a long time to transmit data.
Further, the arrival of the storage key that is required for the main storage at a key access port triggers the registration or storage of the translation results obtained by DAT, in the TLB, and also the release of DAT. Because of this, neither the registration of the translation results nor the release of the DAT can be executed, even if DAT completes an address translation process.
In the main memory access demand that does not require key control protection, the validity check of access is not basically required. In spite of this, when a TLB miss occurs for such a demand, a key access is executed with the main storage, and data is checked by using the arrived storage key, thereby transmitting data. Therefore, a useless waiting time occurs.